1. Field of the Invention
The present invention relates to a clock generator capable of performing operation accurately and being freedom from noise effects, and may be controlled at a low voltage.
2. Description of the Prior Art
A PLL (a phase Locked Loop) has been widely used in many electrical fields. The PLL is a circuit to output multiple clock signals in synchronization with an input clock signal.
Recent microprocessors operate in a higher operation frequency, for example, in a higher clock of several hundreds MHz, so that incorporating of the PLL is indispensable to the microprocessors.
The type of conventional PLLs is an analogue type to control an oscillating frequency by controlling the voltage of a capacitor to store an control voltage of a Voltage Control Oscillator (VCO) based on a charge pump.
However, it is difficult to operate the conventional analogue type PLL under a low voltage and noises greatly affect on the operation of the conventional PLL. Furthermore, it takes a long time for the conventional PLL to reach a stable state and the PLL stops the oscillation when once the supply of the input clock is halted and it take a long time period to restart the operation of the PLL.
In order to eliminate and to solve the drawbacks or the problems described above, conventional techniques provided various methods. For example, the following conventional literature 1 discloses a frequency multiplier generator using digital delay lines.
Literature 1: xe2x80x9cA Portable Clock Multiplier generator Using Digital CMOS Standard Cellsxe2x80x9d, Michel Combes, Karim Dioury, and Alain Greiner, IEEE Journal of Solid State Circuits, Vol.31, No.7, July, 1996.
FIG. 8 is a block diagram showing the configuration of a conventional frequency multiplier. In FIG. 8, the reference number 1 designates a flip flop circuit, 2 denotes a divider, 3 indicates a comparator, 4 designates a control circuit, and 6 and 7 indicate delay circuits, respectively. FIG. 9 is a timing chart showing the operation of the conventional frequency multiplier 10 shown in FIG. 8.
Next, a description will now be given of the operation of the conventional frequency multiple circuit.
In the operation of the conventional frequency multiple circuit 10, there is a possibility to enter a state that the F/F circuit outputs no pulse under the initial state of a delay time of both the delay circuits 6 and 7 as the digital delay line during one period of the timing T1 to the timing T2, as shown in the timing chart of FIG. 9. In this case, there is a drawback that the F/F 1 outputs no multiplied output signal accurately during the one period from the timing T1 to the timing T2 of the input clock shown in FIG. 9 because the output signal M of the divider 2 is asserted during this one period based on a difference between a delay time from the rising edge (Timing T1) of the input clock to the time to negate the output signal M of the divider 2 and a delay time from a falling edge (Timing T1) in the fourth pulse of the multiplied clock output signal as the output signal of the F/F 1 to a time to assert the output signal M of the divider 2.
In addition, the literature 1 showing the frequency multiple circuit 10 as the conventional technique described above has described no phase lock between the input clock and the output signal M of the divider 2. Therefore the literature 1 provides the PLL having an insufficient function.
On the other hand, there is a conventional technique that is obtained by combining a phase locked circuit with the frequency multiple circuit 10 using the digital delay line shown in FIG. 8.
FIG. 10 is a block diagram showing a conventional clock generation circuit 15 that is obtained by combining the phase locked circuit with the frequency multiple circuit 10 using the digital delay line shown in FIG. 8. In FIG. 10, the reference number 10 designates the frequency multiple circuit shown in FIG. 8, 11 denotes a phase locked circuit, 12 indicates a digital delay line forming the phase locked circuit 11, 13 designates a digital counter, and 14 denotes a comparator.
Next, the operation of the conventional clock generation circuit will be explained.
The multiplied clock output signal (or an output clock) provided from the frequency multiple circuit 10 is inputted into the digital delay line 12 in the phase locked circuit 11, then the digital delay line 12 outputs a PLL output signal to outside. The comparator 14 compares the phase of the PLL output signal with the phase of the input clock, and outputs the comparison result to the digital delay line 12 as a feedback signal in order to adjust a delay between both the input clock and the PLL output signal and to coincide the input clock with the PLL output signal in phase.
However, the conventional clock generation circuit 15 having the configuration shown in FIG. 10 has a drawback in which a compensation ability to compensate a delay of the PLL output signal caused by the influence of a voltage value, a temperature value, and so on becomes bad, because it takes many times to reflect the compensation of the period and the phase based on the comparison result obtained by the comparator 3 in the frequency multiple circuit 10 or the comparator 14 in the phase locked circuit 11 when the delay time of the digital delay line 12 becomes longer than the period of the input clock, for example.
FIG. 11 is a timing chart showing the operation of the conventional clock generation circuit 15 shown in FIG. 10. As shown in the timing chart of FIG. 11, when the delay time of the digital delay line 12 in the conventional clock generator 15 is locked in the delay time of twice of the period of the input clock, the comparison result that has been output at the timing T1 from the comparator 3 incorporated in the frequency multiple circuit 10 is output firstly by the phase locked circuit 11 as the PLL output signal only after two periods of the input clock counted from the timing T4. This causes the possibility to decrease the compensation ability and to happen that the delay compensation operation process can not be executed correctly because an incorrect PLL output signal will be generated at the timing T5.
FIG. 12 is a block diagram showing the configuration of the conventional digital delay line 12. In FIG. 12, the reference number 17 indicates a plurality of delay elements forming the digital delay line 12, 18 indicates a selector to select one of the plurality of delay elements 17.
For example, in the techniques disclosed in the literature 1 described above and the following literature 2, the selector 18 selects one of the delay elements 17 in order to adjust the delay time.
Literature 2s: xe2x80x9cMultifrequency Zero-Jitter Delay-Locked Loopxe2x80x9d; Avner Efendovich, et al., IEEE Journal of Solid-State Circuits, Vol.19, No.1, January, 1994.
However, it must be required in the conventional digital delay line having this configuration to switch the entire delay elements 17 even if a delay time of the digital delay line is shorter. This causes to consume un-required electric power.
FIG. 13 is a diagram showing the configuration of another conventional digital delay line. As shown in FIG. 13, the position of an input terminal is changed by using control signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d so that each delay element is selectively activated in order to obtain a desired delay time and also to reduce the power consumption of the digital delay line. However, there is a drawback in the configuration of the digital delay line shown in FIG. 13. For example, when a counter value is changed while the clock generation circuit is operating, namely, when the position of the input terminal is shifted from the node xe2x80x9caxe2x80x9d to the node xe2x80x9cbxe2x80x9d, there is a drawback that unstable electric potential is added on the output xe2x80x9caxe2x80x9d at the timing T8 shown in FIG. 14.
As described above, there is the drawback that in the digital PLL using the digital delay line incorporated in the conventional clock generation circuit, a following phase comparison is performed before the change of the delay time of the digital delay line is reflected to the PLL output signal under an initial state of the multiplied clock output signal as the output signal of the frequency multiple circuit 10, so that the compensation ability to the change of the temperature and the voltage becomes reduced and it becomes difficult to perform the phase lock operation. Furthermore, when all of the delay elements in the digital delay line are switched, the conventional clock generation circuit consumes un-necessary power. Moreover, in the case that the input position of the digital delay line is shifted in order to avoid this un-necessary power consumption, it is difficult to lock the phase accurately when the counter value is changed because a hazard is generated on the output of the digital delay line.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional clock generator, to provide a clock generator whose operation is easily controlled under a low voltage and capable of being free from noises and capable of generating desired clocks even if the supply of input clocks is halted and the period of a lock time is short.
In accordance with a preferred embodiment of the present invention, a clock generator comprises a multiple circuit for receiving an input clock signal and for generating and outputting an output clock signal of a desired multiplied clock signal, wherein an operation of the multiple circuit is initialized when a reset signal is transferred from outside or when the number of the output clock signals provided from the multiple circuit during one period of the input clock signal is less than a predetermined multiple number. It is thereby possible to generate a desired multiplied output clock signal accurately and certainly even if the counter value of the counter has any initial value.
In accordance with a preferred embodiment of the present invention, a clock generator comprising a multiple circuit for receiving an input clock signal and for generating and outputting an output clock signal of a desired multiplied clock signal. In the clock generator, the multiple circuit comprises a first delay circuit for delaying a period or a phase of the output clock signal gradually and a first counter for setting the delay time of the first delay circuit and for controlling an operation of the first delay circuit, wherein the counter value in the first counter is set so that the delay time of the first delay circuit has the minimum value when the operation of the clock generator is initiated or receives a reset signal provided from external. It is thereby possible to generate a desired multiplied output clock signal accurately and certainly
In the clock generator as the preferred embodiment described above, the counter value of the first counter is updated into the minimum value by which a change of the delay time of the first delay circuit has the minimum value. It is also thereby possible to generate a desired multiplied output clock signal accurately and certainly.
In accordance with a preferred embodiment of the present invention, a clock generator comprises a multiple circuit for receiving an input clock signal and for generating and outputting an output clock signal of a desired multiplied clock signal, the multiple circuit comprising a first delay circuit for delaying a period or a phase of the output clock signal gradually, and a first counter for setting the delay time of the first delay circuit and for controlling an operation of the first delay circuit, a phase locked circuit comprising, a second delay circuit for receiving the output clock signal provided from the first delay circuit in the multiple circuit and for delaying the output clock signal by a predetermined time length, and a second counter for setting and controlling the delay time length of the second delay circuit. In the clock generator, the multiple circuit further comprises a third counter in which a second value is set when the initial value of the third counter is the first value and the counter value in the first counter is not changed during a predetermined time period, wherein the counter value of the third counter is changed from the first value to the second value, the counter value of the second counter is set so that the delay time of the second delay circuit becomes equal to or longer than the delay time of the first delay circuit. It is thereby possible to increase the accuracy of the phase lock operation.
In accordance with another preferred embodiment of the present invention, a clock generator comprises a first delay circuit and a second delay circuit, each of the first delay circuit and the second delay circuit comprising a plurality of delay elements connected to each other in series. In this clock generator, one of the plurality of delay elements is selected according to counter values transferred from a first flip flop circuit and a second flip flop circuit corresponding to the first delay circuit and the second delay circuit, and a delay time of each of the first delay circuit and the second delay circuit is determined by the selected delay element and an adjacent delay element next to the selected delay element. It is thereby possible to avoid an occurrence of a failure operation by setting a delay time of a selected delay element and the adjacent delay element of the selected one and to reduce the power consumption of the clock generator and a delay locked loop (DLL).
In the clock generator as another preferred embodiment of the present invention described above, each of the plurality of delay elements comprises two circuits connected in parallel, each of the two circuits comprises n PMOS transistors (n is a positive integer) connected in series and n NMOS transistors connected in series, and gates of a P MOS transistor and a NMOS transistor adjacent to a connection node of both the n PMOS transistors and the n NMOS transistors are connected to each other.
In the clock generator as another preferred embodiment of the present invention described above, each of the first counter and the second counter comprises flip flop circuits and the third counter comprises a flip flop circuit of one bit.